DependSys 2020 - Keynotes
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Keynote Speakers

Mateo Valero

The Future HPC will be open


ABSTRACT: The combination of technology trends and exponential growth of data and compute have ushered in an era of software/hardware co-design to meet the major KPIs for the system. Open hardware is required to participate in this new era and open ISAs like RISC-V enable this capability. Open ISAs provide a final ingredient to produce an open ecosystem for HPC, from software all the way down to the chips. With the momentum behind RISC-V, we believe this ecosystem will dominate this open stack and we are using HPC as the pathfinder to define this new open world. BSC is leading RISC-V projects across two major thrusts that reflect the major compute components in an HPC system: Accelerators and CPUs. BSC is leading EPI Stream 3, a collection of RISC-V accelerators, including a vector accelerator based on the new RISC-V vector extension. This design will evolve into 2 accelerator chiplets (vector accelerator and ML/Stencil accelerator) sharing a common I/O and memory subsystem in EPI Pilot2 (submitted proposal). This pilot will produce chiplets that are coherent, scalable and independent, with only European IP, targeting a small geometry European fab. In additional, BSC is building infrastructure to support future accelerator and CPU designs with the large scale FPGA emulation testbed call MEEP. We see an integrated future of chiplets and HBM memory. We can leverage the HBM memory in the FPGA as well as other hard macros to emulate these systems, at scale. This testbed is also defining the generation of vector accelerators beyond EPI as an example of the capabilities of MEEP as an Software Development Vehicle and pre-silicon validation platform. The BSC is leading several CPU projects to build up the expertise and know-how for the full CPU design cycle, from specification, to chip fabrication, the other pillar of general purpose processing. Finally, we are targeting a high performance 2-way out-of-order processor design with on- and off-chip coherence in the eProcessor project. These projects not only focus on the hardware design, but also the entire software stack to enable the entire open HPC ecosystem.

BIO: Mateo Valero,, obtained his Telecommunication Engineering Degree from the Technical University of Madrid (UPM) in 1974 and his Ph.D. in Telecommunications from the Technical University of Catalonia (UPC) in 1980. He is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focus on high performance architectures. He has published approximately 700 papers, has served in the organization of more than 300 International Conferences and he has given more than 500 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain.

Dr. Valero has been honoured with several awards. Among them, the Eckert-Mauchly Award 2007 by the IEEE and ACM; Seymour Cray Award 2015 by IEEE; Charles Babbage 2017 by IEEE; Harry Goode Award 2009 by IEEE: ACM Distinguished Service Award 2012; Euro-Par Achievement Award 2015; the Spanish National Julio Rey Pastor award, in recognition of research in Mathematics; the Spanish National Award “Leonardo Torres Quevedo” that recognizes research in engineering; the “King Jaime I” in basic research given by Generalitat Valenciana; the Research Award by the Catalan Foundation for Research and Innovation and the “Aragón Award” 2008 given by the Government of Aragón. He has been named Honorary Doctor by the Universities of Chalmers, Belgrade, Las Palmas de Gran Canaria, Zaragoza, Complutense de Madrid, Cantabria,,Granada and the University of Veracruz and CINVESTAV in Mexico. "Hall of the Fame" member of the ICT European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon,November 2008); Honoured with Creu de Sant Jordi 2016 by Generalitat de Catalunya. It is the highest recognition granted by the Government. Honoured with “Condecoración de la Orden Mexicana del Águila Azteca” 2018, highest recognition granted by the Mexican Government.In 2020, Mateo has been recognized with the Outstanding Leadership in HPC award in the HPCWire Readers’ Choice Awards for “being an HPC pioneer since 1990 and the driving force behind the renaissance of European HPC independence”.

In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected Correspondant Academic of the Spanish Royal Academy of Science, in 2006 member of the Royal Spanish Academy of Doctors, in 2008 member of the Academia Europaea and in 2012 Correspondant Academic of the Mexican Academy of Sciences. In 2018, he was elected academic for the Gastronomy Academy in Murcia, Honorary academic of the European Royal Academy of Doctors and Correspondant academic by the Engineering Academy in Mexico. He is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow. In 1998 he won a “Favourite Son” Award of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named their Public College after him.

S. S. Iyengar

Quantum Computing: Pathway for the next decade


ABSTRACT: Quantum computing has come a long way since it was first perceived. Quantum machines have shown potential to revolutionize the design of models pertaining to cryptography, artificial intelligence, machine learning etc. impacting fields like logistics, manufacturing, finance and energy to name a few. Quantum computing will also have a great influence on the way in which our information will be processed and communicated in similar lines to how quantum physics has impacted over the past decade or so.

There are many technical hurdles that has delayed the large-scale adoption of quantum computing some of which include the need for manipulations to be made at nanoscale, special operating environment involving vacuum at cryogenic temperatures etc. However, research conducted over the past decade has given this field significance and the required impetus to be adopted for large scale activities. The use of quantum computers also requires a good understanding of how it differs from the classical computers. Most importantly, quantum computing is not built on bits that take discrete values of zero or one, but on qubits that can be overlays of zeros and ones (i.e., part zero and part one at the same time instant) and qubits do not exist in isolation but become entangled and act as a group. The above-mentioned properties enable qubits to achieve an exponentially higher information density than classical computers.

Quantum Computing and FIU is highly coupled for the last 5 years with outstanding results. The below listed are the contributions and ongoing work in Quantum Computing (QC) at the qubitrest lab, FIU, Florida. Our recent work has been on the following diverse topics: Bidirectional teleportation for underwater quantum communications; Satellite quantum repeaters for a quantum Internet; Satellite quantum communication regardless of the weather; Analysis of five techniques for the internal representation of a digital image inside a quantum processor; Virtual key redistribution in a quantum data security context; Efficient redistribution of keys in a quantum key distribution (QKD) system and others. These topics will pave ways for future investigation and understanding of the field of Quantum computing and bootstrap the adoption of the same in our day to day life. In this talk, we will focus on some of these topics along with the opportunities and requirements for the next decade.

BIO: S. S. Iyengar is a Distinguished University Professor at Florida International University, Miami. Dr. Iyengar is a pioneer in the field of distributed sensor networks/sensor fusion, computational aspects of robotics and high-performance computing. He has published over 600 research papers and has authored/edited 22 books published by MIT Press, John Wiley & Sons, Prentice Hall, CRC Press, Springer Verlag, etc. These publications have been used in major universities all over the world. He has many patents and some patents are featured in the World’s Best Technology Forum in Dallas, Texas. His research publications are on the design and analysis of efficient algorithms, parallel computing, sensor networks, and robotics. During the last four decades, he has supervised over 65 Ph.D. students, 100 Master’s students, and many undergraduate students who are now faculty at Major Universities worldwide or Scientists or Engineers at National Labs/Industries around the world. He has also had many undergraduate students working on his research projects. Recently, Dr. Iyengar received the Test of Time Award for his seminal work in Brooks-Iyengar Algorithm.

Dr. Iyengar is a member of the European Academy of Sciences, a Fellow of IEEE, a Fellow of ACM, a Fellow of AAAS, a Fellow of the National Academy of Inventors NAI and a Fellow of Society of Design and Process Program (SPDS), Fellow of Institution of Engineers (FIE), a Fellow of the American Institute for Medical and Biological Engineering (AIMBE), was awarded a Distinguished Alumnus Award of the Indian Institute of Science, Bangalore, and the IEEE Computer Society Technical Achievement for the contributions to sensor fusion algorithms, and parallel algorithms. He also received the IBM Distinguished Faculty Award, NASA Fellowship Summer Awards at Oakridge National Lab and the Jet Propulsion Laboratory. He is a Village Fellow of the Academy of Transdisciplinary Learning and Advanced Studies in Austin, Texas, 2010.

He has received various national and international awards including the Times Network NRI (Non-Resident Indian) of the Year Award for 2017, the National Academy of Inventors Fellow Award in 2013, the NRI Mahatma Gandhi Pradvasi Medal at the House of Lords in London in 2013, a Lifetime Achievement Award conferred by International Society of Agile Manufacturing (ISAM) in recognition of his illustrious career in teaching, research and administration and a lifelong contribution to the fields of Engineering and Computer Science at Indian Institute of Technology (BHU). In 2012, Iyengar and Nulogix were awarded the 2012 Innovation-2-Industry (i2i) Florida Award. Iyengar received a Distinguished Research Award from Xaimen University, China for his research in Sensor Networks, Computer Vision and Image Processing. Iyengar's landmark contributions with his research group include the development of grid coverage for surveillance and target location in distributed sensor networks and the Brooks Iyengar fusion algorithm. He has also been awarded Honorary and Doctor of Science and Engineering Degree. He serves on the advisory board of many corporations and universities around the world. He has served on many National Science Boards such as NIH - National Library of Medicine in Bioinformatics, National Science Foundation review panel, NASA Space Science, Department of Homeland Security, Office of Naval Security, and many others. His contribution to the US Naval Research Laboratory was a centerpiece of a pioneering effort to develop image analysis for science and technology and to expand the goals of the US Naval Research Laboratory.

The impact of his research contributions can be seen in companies and National Labs like Raytheon, Telecordia, Motorola, the United States Navy, DARPA, and other US agencies. His contribution in DARPAS's program demonstration with BBN, Cambridge, Massachussetts, MURI, researchers from PSU/ARL, Duke, University of Wisconsin, UCLA, Cornell university and LSU has been significant.

He is also the founding Editor of the International Journal of Distributed Sensor Networks. He has been on the editorial board of many journals and is also a PhD Committee Member at various universities, including CMU, Duke University, and many others throughout the world. He is presently the Editor of ACM Computing Surveys and other journals. He is also the founding director of the FIU’s Discovery Laboratory. His research work has been cited extensively. His fundamental work has been transitioned into unique technologies. All through his four-decade long professional career, Dr. Iyengar has devoted and employed mathematical morphology in a unique way for quantitative understanding of computational processes for many applications.

Sumi Helal

Sentience-Efficient Edge Computing for City-Scale IoT Deployments


ABSTRACT: Recent advances in IoT and pervasive and ubiquitous computing provide a glimpse into the future of our planet and reveal exciting visions of smart many things: smart cities, smart homes, smart cars, in addition to smart spaces such as malls, workplaces, hotels, schools, and much more. Driven by a technological revolution offering “low-power many things and wireless almost everything”, we could, in only a decade, envision and prototype impressive smart space systems that improve quality of life, enhance awareness of resources and the environment, and enrich users’ experience. But prototyping is one thing; actual large-scale deployments are another. The massive scale of sensors and IoT devices that will be deployed in highly populated smart cities of the future will be mind-bugling. Without a carefully-thought ecosystem and a scalable architecture in place, it will be extremely difficult to manage or program such an expanding and massive IoT. In this talk, I will start by raising the thought of how can we estimate the Value of the IoT as we once estimated the value of the network. I will then introduce our recent work - the Cloud-Edge-Beneath (CEB) architecture, and present its salient scalability features. I will also present CEB’s bi-directional waterfall optimization framework and show how it leads to “sentience-efficiency” – a new paradigm for realizing aggressive energy-efficiency. I will then present an event-driven programming model based on CEB and show how the model and CEB, combined, foster a much-needed IoT programmability ecosystem. Finally, I will present a validation study demonstrating CEB’s scaling behavior in face of IoT expansions (sensors and applications) and under dynamically increasing loads.

BIO: Sumi Helal is a Professor in the Computer & Information Science and Engineering Department at the University of Florida, USA, and Director of its Mobile and Pervasive Computing Laboratory. He co-founded and directed the Gator Tech Smart House, a real-world deployment project that aimed at identifying key barriers and opportunities to make the Smart Home concept a common place (creating the "Smart Home in a Box" concept). His active areas of research focus on architectural and programmability aspects of the Internet of Things, and on pervasive/ubiquitous systems and their human-centric applications with special focus on smart spaces, proactive health/wellness, patient empowerment and e-coaching, and assistive technology in support of personal health, aging, disabilities, and independence. Professor Helal served as the Editor-in-Chief of IEEE Computer (2015-2018), the Computer Society's flagship and premier publication. Professor Helal is a Boilermaker (Ph.D., Purdue University, class of 1991), Fellow of the IEEE, Fellow of the IET, Fellow of the AAAS, and a member of Academia Europaea. He is also the 2020 IEEE Computer Society President-Elect nominee. Contact him at

Geoffrey Charles Fox

Big Data Systems and HPC


ABSTRACT: We discuss Big Data Systems noting different requirements for data science with compute-intensive execution of deep/machine learning and data engineering with many pre-processing, post-processing, and data management tasks. High performance computing HPC will be critical especially in the data science component. We need to integrate the Java (data engineering) C++ (deep learning) and Python ecosystems.

This architecture suggests a cloud of modest-sized AI-accelerated systems in a sea of commodity servers. We discuss how Twister2 and Cylon linked to a wealth of other capabilities help to address this.

Deep Learning (DL) is rapidly replacing other AI (ML) and we give 3 examples i) MDS Multidimensional scaling for dimension reduction ii) Surrogates for simulations and data analytics; iii) Spatial time series where we give application examples from COVID-19 daily data, solutions of ordinary differential equations, and other fields of science generating geospatial time series.

Most computing could be done on the HPC hybrid clouds described in the first paragraph with the largest scale simulations performed on (exascale) supercomputers deriving the surrogates that allow many simulations to be performed on smaller machines. Recently 2 Gordon Bell and the CASP awards went to molecular science simulations enhanced by deep learning surrogates which highlights new modes of science discovery. We review the core AI issues needed to advance the study of surrogates including neural and hyperparameter search, mapping of patterns to meta-surrogates, uncertainty quantification, and minimization of training set size.

BIO: Fox received a Ph.D. in Theoretical Physics from Cambridge University, where he was Senior Wrangler. He is now a distinguished professor of Engineering, Computing, and Physics at Indiana University, where he is the director of the Digital Science Center. He previously held positions at Caltech, Syracuse University, and Florida State University after being a postdoc at the Institute for Advanced Study at Princeton, Lawrence Berkeley Laboratory, and Peterhouse College Cambridge. He has supervised the Ph.D. of 73 students and published around 1500 papers (550 with at least ten citations) in physics and computing with a hindex of 83 and over 39000 citations. He received the High-Performance Parallel and Distributed Computing (HPDC) Achievement Award and the ACM - IEEE CS Ken Kennedy Award for Foundational contributions to parallel computing in 2019. He is a Fellow of APS (Physics) and ACM (Computing) and works on the interdisciplinary interface between computing and applications. He is involved in several projects to enhance the capabilities of Minority Serving Institutions. He has experience in online education and its use in MOOCs for areas like Data and Computational Science. He is active in the Industry consortium MLPerf. Contact him at More details can be found at

Honggang Wang

Towards Smart and Secure Wireless Health


ABSTRACT: Wireless health is the use of Internet, sensing, wireless communications and intelligent techniques in support of healthcare applications. Wireless body area networks (WBANs) with various types of biomedical sensors is one of major infrastructures of connected health and provide an opportunity to address issues in rapidly increasing wireless health applications. However, there are significant challenges in the area, such as improving the performance of WBANs, analytics of large and continuous physiological data collected from biomedical sensors and predictive modeling, and securing data transmission and protecting data privacy, especially in mobile and wireless environments. In this talk, I will introduce two case studies in the related area: (1) developing a wearable biosensor system for the remote detection of life threatening events in infants; (2) a security system to support reliable and secured data transmissions over WBANs.

BIO: Honggang Wang is a professor of Electrical and Computer Engineering at UMass Dartmouth. He received the "Scholar of The Year" award (only one per year) in 2016 from UMass Dartmouth. His research interests include Internet of Things (IoT), Wireless Health, Body Area Networks (BAN), Cyber and Multimedia Security, Mobile Multimedia and Cloud, Wireless Networks and Cyber-physical System, and BIG DATA in mHealth. He has published more than 200 papers in his research areas. He was an invited participant by National Academic Engineering (NAE) for 2017 German-American Frontiers of Engineering Symposium, as one of about 50 outstanding young engineers from US companies, universities, and government labs. He serves as the steering committee Co-chair of IEEE conference on Connected Health (CHASE) and TPC co-chair of IEEE CHASE 2016, which is a leading international conference in the field of connected health. He has also been serving as the Editor in Chief (EiC) for IEEE Internet of Things journal since 2020, and Associate Editors for IEEE Transactions on Big Data and IEEE Transactions on Circuits and Systems for Video Technology. He was the past Chair (2018-2020) of IEEE Multimedia Communications Technical Committee and is the Chair of IEEE eHealth Committee (2020-2021). He is an IEEE Distinguished Lecturer (ComSoc, 2019-2020) and an IEEE Fellow (class 2021).

Bingsheng He

Large Graph Processing on Heterogeneous Architectures: Systems, Applications and Beyond


ABSTRACT: Graphs are de facto data structures for many data processing applications, and their volume is ever growing. Many graph processing tasks are computation intensive and/or memory intensive. Therefore, we have witnessed a significant amount of effort in accelerating graph processing tasks with heterogeneous architectures like GPUs, FPGAs and even ASIC. In this talk, we will first review the literatures of large graph processing systems on heterogeneous architectures. Next, we present our research efforts, and demonstrate the significant performance impact of hardware-software co-design on designing high performance graph computation systems and applications. Finally, we outline the research agenda on challenges and opportunities in the system and application development of future graph processing. More details about our research can be found at

BIO: Dr. Bingsheng He is currently an Associate Professor and Vice-Dean (Research) at School of Computing, National University of Singapore. Before that, he was a faculty member in Nanyang Technological University, Singapore (2010-2016), and held a research position in the System Research group of Microsoft Research Asia (2008-2010), where his major research was building high performance cloud computing systems for Microsoft. He got the Bachelor degree in Shanghai Jiao Tong University (1999-2003), and the Ph.D. degree in Hong Kong University of Science & Technology (2003-2008). His current research interests include cloud computing, database systems and high performance computing. His papers are published in prestigious international journals (such as ACM TODS and IEEE TKDE/TPDS/TC) and proceedings (such as ACM SIGMOD, VLDB/PVLDB, ACM/IEEE SuperComputing, ACM HPDC, and ACM SoCC). He has been awarded with the IBM Ph.D. fellowship (2007-2008) and with NVIDIA Academic Partnership (2010-2011). Since 2010, he has (co-)chaired a number of international conferences and workshops, including IEEE CloudCom 2014/2015, BigData Congress 2018 and ICDCS 2020. He has served in editor board of international journals, including IEEE Transactions on Cloud Computing (IEEE TCC), IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), IEEE Transactions on Knowledge and Data Engineering (TKDE), Springer Journal of Distributed and Parallel Databases (DAPD) and ACM Computing Surveys (CSUR). He has got editorial excellence awards for his service in IEEE TCC and IEEE TPDS in 2019.



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